Description

XiangShan (Open-source high-performance RISC-V processor) commit edb1dfaf7d290ae99724594507dc46c2c2125384 (2024-11-28) contains an improper exceptional-condition handling flaw in its CSR subsystem (NewCSR). On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR addresses may trigger an illegal-instruction exception but fail to reliably transfer control to the configured trap handler (mtvec), causing control-flow disruption and potentially leaving the core in a hung or unrecoverable state. This can be exploited by a local attacker able to execute code on the processor to cause a denial of service and potentially inconsistent architectural state.

Weaknesses 1

References 4

• docs.riscv.org https://docs.riscv.org/reference/isa/priv/machine.html
• docs.riscv.org https://docs.riscv.org/reference/isa/priv/priv-csrs.html
• github.com https://github.com/OpenXiangShan/XiangShan/issues/3959
• github.com https://github.com/OpenXiangShan/XiangShan/pull/3966

Remediation