CVE-2025-63384

MEDIUM EPSS 18.3%
Published Nov 10, 20257mo ago · Modified Jun 17, 20262w ago
6.5 CVSS 3.1
Medium
Find Similar
Published Nov 10, 2025 7mo ago
Last Modified Jun 17, 2026 2w ago

Description

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

CVSS Details

Base Score
6.5
Exploitability
2.8
Impact
3.6
Vector string
CVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N
Attack Vector Network
Attack Complexity Low
Privileges Required Low
User Interaction None
Scope Unchanged
Confidentiality High
Integrity None
Availability None

Threat Intelligence

EPSS Exploit Probability
18.3% percentile
Exploit & Patch Status
Public Exploit Known
No Patch Available

Weaknesses 1

CWE-266

Affected Products 1

VendorProductVersionRange
chipsalliancerocketchip* ≤1.6

References 2

  • github.com https://github.com/107040503/RISC-V-Vulnerability-Disclosure_SRET
    ExploitThird Party Advisory
  • github.com https://github.com/chipsalliance/rocket-chip.git
    Product

Remediation

No remediation data recorded yet

Check vendor advisories and the NVD entry for patch availability.