CVE-2025-45006
CRITICAL EPSS 30.9%
Published Jul 1, 20251y ago · Modified Jun 17, 20262w ago
9.1 CVSS 3.1
Published Jul 1, 2025 1y ago
Last Modified Jun 17, 2026 2w ago
Description
Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.
CVSS Details
Base Score
Exploitability
Impact
Vector string
CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H Attack Vector Network
Attack Complexity Low
Privileges Required None
User Interaction None
Scope Unchanged
Confidentiality High
Integrity None
Availability High
Threat Intelligence
EPSS Exploit Probability
30.9% percentile
Exploit & Patch Status
No Known Exploit
No Patch Available
Weaknesses 1
CWE-266
References 3
- github.com https://github.com/chipsalliance/rocket-chip.git
- github.com https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md
- lf-riscv.atlassian.net https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications
Remediation
No remediation data recorded yet
Check vendor advisories and the NVD entry for patch availability.