CVE-2025-0647
HIGH EPSS 4.9%
Published Jan 14, 20265mo ago · Modified Jun 17, 20261w ago
7.9 CVSS 3.1
Published Jan 14, 2026 5mo ago
Last Modified Jun 17, 2026 1w ago
Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
CVSS Details
Base Score
Exploitability
Impact
Vector string
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N Attack Vector Local
Attack Complexity Low
Privileges Required High
User Interaction None
Scope Changed
Confidentiality High
Integrity High
Availability None
Threat Intelligence
EPSS Exploit Probability
4.9% percentile
Exploit & Patch Status
No Known Exploit
No Patch Available
Weaknesses 1
CWE-226
Affected Products 22
| Vendor | Product | Version | Range |
|---|---|---|---|
| arm | c1-ultra_firmware | * | any |
| arm | c1-ultra | * | any |
| arm | c1-premium_firmware | * | any |
| arm | c1-premium | * | any |
| arm | cortex-a710_firmware | * | any |
| arm | cortex-a710 | * | any |
| arm | cortex-x2_firmware | * | any |
| arm | cortex-x2 | * | any |
| arm | cortex-x3_firmware | * | any |
| arm | cortex-x3 | * | any |
| arm | cortex-x4_firmware | * | any |
| arm | cortex-x4 | * | any |
| arm | cortex-x925_firmware | * | any |
| arm | cortex-x925 | * | any |
| arm | neoverse-v2_firmware | * | any |
| arm | neoverse-v2 | * | any |
| arm | neoverse-v3_firmware | * | any |
| arm | neoverse-v3 | * | any |
| arm | neoverse-v3ae_firmware | * | any |
| arm | neoverse-v3ae | * | any |
| arm | neoverse-n2_firmware | * | any |
| arm | neoverse-n2 | * | any |
References 2
- developer.arm.com https://developer.arm.com/documentation/111546
- graph.volerion.com https://graph.volerion.com/view?ID=CVE-2025-0647
Remediation
No remediation data recorded yet
Check vendor advisories and the NVD entry for patch availability.