CVE-2024-24853
HIGH EPSS 14.0%
Published Aug 14, 20241y ago · Modified Jun 17, 20262w ago
7.3 CVSS 4.0
Published Aug 14, 2024 1y ago
Last Modified Jun 17, 2026 2w ago
Description
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
CVSS Details
Base Score
Exploitability
Impact
Vector string
CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:P/VC:H/VI:H/VA:H/SC:H/SI:H/SA:H/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X Attack Vector Local
Attack Complexity High
Privileges Required High
User Interaction P
Scope X
Threat Intelligence
EPSS Exploit Probability
14.0% percentile
Exploit & Patch Status
No Known Exploit
No Patch Available
Weaknesses 1
CWE-696
References 1
- intel.com https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01083.html
Remediation
No remediation data recorded yet
Check vendor advisories and the NVD entry for patch availability.